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    社会招聘


    职位描述


    Perform and/or lead various DFT tasks for the creation of SOC chips. The areas of focus will be to architect, develop and optimize structured test solutions using DFT insertion and ATPG tools as well as BIST for memories, etc. He will be responsible for architecting and integrating DFT structures into RTL and netlists to deliver reliable, efficient and high quality manufacturing test coverage:

    • Architect DFT strategies for complex SOC designs;
    • Generate and insert Scan, Memory BIST, Boundary Scan, Test Compression etc.;
    • Generate ATPG vectors for stuck-at, delay fault and other types;
    • Determine, analyze and enhance fault coverage to achieve target test quality;
    • Interface with ATE test engineer.

    岗位要求


    • BS/MS in Electrical or Computer Engineering with 5+ years ’ related experience in designing DFT for SOCs;
    • Familiar with Mentor Tessent tool;
    • Strong working knowledge in SoC design and design methodology;
    • Skill and efficiency in scripting using common UNIX scripting languages such as TCL, Perl, csh;
    • Excellent RTL and gate level debug skills;
    • Formal analysis/STA Experience.

    申请职位

    职位描述


    • Implement block level physical design from netlist to GDS, including floorplan, placement, CTS, routing, parasitic extraction, STA, Power analysis, Crosstalk analysis, physical verification and ECO;
    • Solve block level timing, congestion, and IR/EM issues;
    • Work with top level design engineers to achieve different sign-off requirements;
    • Develop block level P&R flow;
    • Work on or support full-chip implementation and design closure in different areas, such as Floorplan, IREM, and PV.

    岗位要求


    • Bachelor or master degree in Engineering (Microelectronics, Electronics);
    • 5+ years of hands on experience in large scale ASIC chip physical design;
    • Experience?with common EDA tools flow, ie: Innovus/Prime Time/Calibre;
    • Successful tape out experience is a plus;
    • Good teamwork and communication skills;
    • Familiar with scripting/programming (TCL, Perl, shell script, Python);
    • Good English reading and writing skills.

    申请职位

    职位描述


    • Working with chip design teams to validate the performance of high speed Serdes?chips;
    • Perform Serdes signal integrity related measurement on RD phase, including S parameters, impedance, eyes, all kinds of jitters and noise, JTOL, bathtub curve, phase jitter;
    • Perform the compliance test according to the PCIe and 802.3 standards;
    • Writing Python codes to conduct automatic measurement on Serdes transmitter, receiver and system board;
    • Debug problems together with chip design teams.

    岗位要求


    • BSEE with 7 years of applicable work?experience or MSEE with 5 years of experience;
    • Strong knowledge in measurement theory and measurement skills?(VNA, TDR, Real Time Scope, BERT);
    • Proficient theory on series equalization, Serdes circuit (FFE/CTLE/DFE) and jitter separation;
    • Very familiar with PCIe standards. Knowing 25G/56G/112G Ethernet and CEI is a plus;
    • Good skills on Python coding;
    • Experience with at least one PCB layout tools: Cadence Allegro, Mentor Expedition or Altium Protel.

    申请职位

    职位描述


    • Participate ASIC digital verification for various IP/SoC projects;
    • Create verification plans with designers;
    • Develop DV architecture and verification environment;
    • Verification execution and sign-off.

    岗位要求


    • Excellent team working style;
    • Solid IP/SoC verification background;
    • Mass production for verified IP/SoC;
    • Master with 2+ years of working experience in ASIC digital verification;
    • Production experience in verification strategies and testplans;
    • Familiar with System Verilog/UVM for testbench creation, debug, reuse, constrained-random stimulus and functional coverage;
    • Production experience in ARM buses, such as AXI/AMBA/APB is a plus;
    • Familiar with verification tools;
    • Experiences in Dsp,Core, trace&debug,Soc is a plus;
    • Familiar with Linux, csh/Python or any script languages;
    • Good English reading and writing skills.

    申请职位

    职位描述


    • Lead physical design of projects, build and manage physical design team;
    • Coordinate with different teams to close design issues, such as front-end team, DFT team, and package team;
    • Responsible for achievable die size, meet design requirements, drive design closure and sign-off checks;
    • Responsible for full chip floorplan & partition, pin assign, feedthrough & repeater insertion; release floorplan to block level implementation;
    • Develop top level physical design flow.

    岗位要求


    • Bachelor or Master Degree in Engineering (Microelectronics, Electronics);
    • 10+ years of hands on experience in large scale ASIC chip physical design;
    • Experienced with large scale full chip floorplan;
    • Familiar with top-down design methodology;
    • Experience on project and team management;
    • Good teamwork and communication skills;
    • Proficient with scripting/programming (TCL, Perl, shell script, Python);
    • Language: Good English read/write.

    ?

    申请职位

    职位描述


    • Lead the DFT team to support complex SoC design;
    • Define, prototype and deploy DFT architectures and efficient DFT flows;
    • Work with design team to guarantee high DFT coverage;
    • Work with test engineering team in patterns handoff and debug;
    • Work with design and system team for post-silicon validation.

    岗位要求


    • Master degree with 8+ years of industry experience in DFT;
    • Good understanding of logic design, synthesis, static timing analysis and CDC;
    • Knowledge of industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time;
    • Experience in developing DFT specifications and driving DFT architecture and methods for designs;
    • Past experience as a team lead (direct management experience preferred);
    • Positive mindset, self-driven and good team player;
    • Excellent written and oral communication skills in both Chinese and English.

    申请职位

    职位描述


    • Build SoC/IP level Spyglass/Synthesis/Timing Analysis/Formality Check/CDC flow;
    • Do SoC/IP level synthesis/timing analysis/formality check/CDC check;
    • Deliver constraints and closely co-work timing closure with P&R;
    • Take some block level RTL coding.

    岗位要求


    • MSEE with 3+ year experience in digital design experience;
    • Relevant experience in complex timing closure;
    • Be familiar with DC/PT/formality check tools;
    • Be familiar with Scripts language such as Tcl, Perl, etc.;
    • RTL coding experience is a plus.

    申请职位

    职位描述


    • Serdes communication system algorithm design;
    • Digital signal processing of mixed-signal system;
    • Analog circuit behavior modeling;
    • Support verification of mixed-signal system.

    岗位要求


    • MS or PhD degree in EE or Communication with an emphasis on digital signal processing and one of the following: communications systems or analog/mixed-signal integrated circuit design;
    • Familiar with commercial wireline or wireless communication specifications;
    • Familiar with the following programming languages: Matlab/simulink, C/C++;
    • Familiar with digital signal processing algorithm and practical implementation skills including?adaptive signal processing, multi-rate signal processing, linear regression, knowledge of concepts such as cost functions, etc.;
    • Experience in algorithm development for software and/or hardware;
    • Strong communication skills and ability to work in distributed development environment.

    申请职位

    职位描述


    • Writing?micro-architecture definition/IC design spec;
    • RTL coding for logic modules;
    • Simulation/Verification of functionalities at both module level and top level;
    • Do?module level synthesis/timing analysis;
    • Writing complete design/verification reports;
    • Silicon debug of the related module functionalities;
    • Writing test patterns for production tests.

    岗位要求


    • MSEE with minimum 2 year experience of digital design experience;
    • Relevant experience in high-speed and low power digital design is must;
    • Solid knowledge in digital design building blocks (eg. Data-path, Synchronizer, FIFO, etc.);
    • Strong skills of Verilog RTL coding and verification and debug;
    • Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.;
    • Relevant experience in DDR interface design is a plus;
    • Self-motivated and team player.

    申请职位

    职位描述


    • Support?EDA design flow and EDA tool, including digital and analog design flow;
    • Support timing characterization flow for stand cell, I/O, memory, analog IP;
    • Support?TCAD to setup and debug foundry technology files;
    • Perl/SKill/TCL script support.

    岗位要求


    • BSEE with minimum 1 year or MSEE with minimum 1 year of experience;
    • Familiar with EDA design flow for mixed-signal design;
    • Familiar with Computer languages such as C, C++, perl/TCL/C-shell.

    ?

    申请职位

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